1. Field of the Invention
The present invention relates to a method and system for inspecting the quality of a semiconductor device which has circuits containing MISFETs and functional cells. More particularly, the present invention is concerned with inspecting semiconductor device quality based on measurement of static current in the semiconductor device, and a method for producing a semiconductor device inspected by the method of the present invention.
2. Description of the Related Art
Lately, as semiconductor devices have become highly integrated and have a high degree of functionality, it has become very difficult to carry out tests for determining the quality of the semiconductor devices. For example, while defects on circuits may be relatively easily detected on a printed board in which the circuits are highly integrated since it is possible to carry out a test using endpoints such as individual ICs and resistors, in addition to I/O terminals, to confirm function, the inside of a semiconductor device like an LSI (large scale integration) circuit, which is highly integrated, is wholly a "black box" and the internal operation of an LSI circuit can only be observed through external terminals. However, the function or operation of such circuits still need to be confirmed and it needs to be determined whether they are good or bad, since equipment having a defective LSI circuit will not perform in accordance with its intended design function. Accordingly, it has become an important issue not only for users but also for circuit designers and semiconductor device producers, as to how to accurately inspect a single LSI circuit.
In order to confirm that such a semiconductor device is accurately designed and is produced without defects, the circuit designer creates function test patterns using logical simulations. The function test patterns do not always have a high fault-detection rate, so the designer has to devise various test circuit structures or add test patterns. It is possible to create test patterns that can inspect all combinations of inputs and all internal states to confirm the function of an LSI circuit. However, given a device with n inputs and m internal registers, 2.sup.n+m test patterns are required to inspect the device based on the aforementioned method. Therefore, it requires an enormous number of test patterns even for a device only having 10 inputs and 10 internal registers.
Experience has shown that the cost of creating test patterns having a high fault-detection rate is proportional to from the square to the cube of the number of gates. Furthermore, it is not easy to create test patterns having a high fault-detection rate for a highly functional and large integrated scale type of semiconductor device. To this end, several easy-to-test designs in which testing is taken into consideration during the designing stage have been proposed, and semiconductor devices are being designed based on these easy-to-test designs.
Problems in facilitating the tests are roughly divided into two categories: controllability and observability. Controllability relates to how gates within the circuit can be driven during the inspection process, where it is desirable to be able to turn all of the gates ON/OFF in order to detect an abnormality in the circuit. Observability relates to how to observe the abnormality in the operation of the gates. That is, it means that a fault in the gates cannot be detected as a fault unless it is transmitted to an observation point. In order to accurately carry out inspection of the semiconductor device, test patterns and circuit design that satisfy both controllability and observability are necessary.
One of the methods adopted for highly integrated semiconductor devices among such settings for facilitating testing is a scan-pass method as shown in FIG. 26. This method allows division of circuits structured within a semiconductor device into several combinational circuits C1, C2, and C3 by separating them from normal connections during inspection. The combination circuits C1, C2, and C3 are then driven and inspected one by one. Although this method requires many flip-flops F.sub.l to F.sub.m for dividing and inspecting the circuits, the controllability and observability of the test patterns may be enhanced since the control and observation points are increased in response to the added number of flip-flops, F.sub.l to F.sub.m, in addition to j inputs I.sub.l to I.sub.j and n outputs O.sub.l to O.sub.n. Furthermore, a test pattern group used for inspecting the semiconductor device for which such a design technique has been adopted, is a set of patterns, that allow observation of a fault, selected from a test pattern group automatically created and selected based on an algorithm D and a random number method through fault simulations, to enhance the fault detection rate.
To increase the number of observation points, a cross-check method that connects the outputs of all gates to terminals for testing has also been proposed. The use of this method allows an improved fault-detection rate, however, it has the disadvantage that the number of gates, and the area of the semiconductor device, are increased due to additional circuits like flip-flops and terminals. While miniaturization of semiconductor devices is being promoted by highly integrating and providing a high degree of functionality to semiconductor devices, the circuits necessary for inspecting those devices are being increased and the area occupied by the additional circuits is also being increased within the device.
There is also another disadvantage in that the production cost of the semiconductor device is increased by installing such additional circuits. There is still another disadvantage in that operation of the device cannot be confirmed by an inspection carried out under a state different from a state of the circuit actually used, since the inspection is carried out using additional circuits.
Accordingly, in light of the aforementioned disadvantages, an object of the present invention is to realize a method and a system that allow effective inspection of a fault on circuits formed on the semiconductor device in a relatively short time. It is a further object of the present invention to suppress the increase in area of the semiconductor device due to additional circuits and to allow inspection of the semiconductor device in real operation.